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SP5026 1.0GHz 3-Wire Bus Controlled Synthesizer
Data Sheet Features
* * * * * * * * * * * Complete 1.OGHz Single Chip System Dual Standard 62.5kHz or 31.25 kHz Step Size Low power Consumption (5V 40mA) Function Compatible with Toshiba TD6380 and TD6381* Pin Compatible with SP5510 Low Radiation Varactor Drive Amplifier Disable Charge Pump Disable Single Port 18/19 Bit Serial Data Entry Four Controllable Outputs ESD Protection
DS5776 Issue 2 December 2002
Ordering Information SP5026 DP 18-lead plastic package) SP5026S MP (16-lead miniature plastic package)
Description
The SP5026 is a programming variant of the SP5510, allowing the design of one tuner with either 12C bus or 3-wire bus format depending on which device is inserted. The SP5026, when used with a TV varicap tuner, forms a complete phase locked loop tuning system. The circuit consists of a divider-by-8 prescaler with its own preamplifier and at 5-bit programmable divider controlled by a serially-loaded data register. Four open-collector outputs, each independently programmable, are included. The device has two modes of operation, selected by the "mode select" input. In mode 1, the comparison frequency is 7.8125kHz and the programmable divider MSB is bypassed; mode 2 comparison frequency is 3.90625kHz. The comparison frequencies are both obtained from a 4MHz crystal controlled on-chip oscillator.
See notes on pin compatibility Normal ESD handling procedures should be observed
Applications
* * * Satellite TV when combined with SP4902 2.5GHz Prescaler Cable tuning systems VCRs
Figure 1 - Block Diagram
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SP5026
Data Sheet
The comparator has a charge pump output with an amplifier stage around which feedback may be applied. Only one external transistor is required for varicap line driving.
Figure 2 - Pin Connections - Top View
Functional Description
The SP5026 contains all the elements necessary, with the exception of reference crystal, loop filter and external high voltage transistor to control a voltage controlled local oscillator, so forming a PLL frequency synthesized source. The system is controlled by a microprocessor via a standard data, clock enable three-wire bus. The data load normally consists of a single word, which contains the frequency and port information and is only transferred to the internal data shift register during an enable high period. The clock input is disabled during enable low periods. New data words are only accepted by the internal data buffers from the shift register on a negative transition of the enable, so giving improved fine tune facility for digital AFC etc. The data sequence and timing follows the format shown in Figure 3. The frequency is set by loading the programmable divider with the required 14/15 bit divisor word. The output of the divider, FPD, is fed to the phase comparator where it is compared in phase and frequency domain to the internal generated comparison frequency, FCOMP.
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Data Sheet
SP5026
The FCCOMP is obtained by dividing the output of an on-chip crystal controlled oscillator. The crystal frequency used is generally 4MHz, which gives an FCOMP of 3.90625kHz/7.815kHz and, when multiplied back up to the synthesized LO, gives a minimum step size of 31.25kHz/62.5kHz, respectively. The programmable divider is preceded by an input RF preamplifier and high speed, low radiation prescaler. The preamplifier is arranged to be self oscillating, so giving excellent input sensitivity. The input sensitivity and impedance are shown in Figure 5 and Figure 7 respectively. The SP5026 contains an improved lock detect circuit which generates a flag when the loop has attained lock. "Out of Lock" is indicated by high impedance state. The SP5026 contains 4 general purpose open collector outputs, ports P1-P4, which are capable of sinking at least 10mA. These outputs are set by the remaining four bits within the normal data word.
Pin Compatibility
The SP5026 may by used in SP5510 applications which require 3-wire bus as opposed to 12C bus data format. In SP5510 applications where the reference crystal is connected to pin 3, a small modification is required to ground the crystal as shown in Figure 4. Appropriate connections to the mode select input (pin 3) must also be made. In mode 1 (pin 3 "HIGH") the SP5026 is programming and step size compatible with the Toshiba TD6380, and in mode 2 (pin 3 "LOW") it is compatible with the TD6381.
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SP5026
Data Sheet
Figure 3 - Data Format and Timing
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Zarlink Semiconductor Inc.
Data Sheet
SP5026
Figure 4 - Typical Application (FSTEP = 31.25kHz)
Figure 5 - Typical Input Sensitivity
Zarlink Semiconductor Inc.
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SP5026
Data Sheet
Figure 6 - Input/Output Interface Circuits
Figure 7 - Input/Output Interface Circuits
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Zarlink Semiconductor Inc.
Data Sheet
SP5026
Figure 8 - Typical Input Impedance
Electrical Characteristics
Electrical Characteristics Table Value Characteristics Supply current Prescaler input voltage Prescaler input impedance Input capacitance High level input voltage High level input voltage Low level input voltage High level input current Low level input current Low level input current High level input current Low level input current 4,5,10 3 3,4,5,10 4,5,10 5 4,10 3 3 3 4 0 Symbol ICC Pin Min. 14 15,16 15,16 12.5 50 2 VCC VCC 0.7 1 5 250 150 1 Typ. 40 Max. 55 300 mA mVRMS pF V V V A A A A A VIN = 5.5V, VCC = 5.5V VIN = 0V, VCC = 5.5V VIN = 0V, VCC = 5.5V VIN = 5.5V, VCC = 5.5V VIN = 0V, VCC = 5.5V VCC = 5V 50MHz to 1GHz sinewave Units Conditions
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SP5026
Electrical Characteristics Table (continued) Value Characteristics Clock input hysteresis Clock rate Data set up time Data hold time Enable set up time Enable hold time Clock-to-enable time Charge pump output current Charge pump output leakage current Drift due to leakage Charge pump drive output current Charge pump amplifier gain Oscillator temperature stability Oscillator stability with supply voltage Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator source impedance Port leakage current Lock leakage current Varactor Drive Amp Disable Charge Pump Disable 2 2 6-9 11 10 4 -350 -350 10 40 -400 10 10 18 1 6400 2 2 200 ppm/
oC
Data Sheet
Symbol
Pin Min. 5 5 Typ. 0.4 0.5 300 600 300 600 300 +150 +5 5 Max.
Units V MHz ns ns ns ns ns A nA mV/s mA
Conditions
t2 t3 t1 t5 t4
4 4 10 10 10 1 1
See Figure 3 See Figure 3 See Figure 3 See Figure 3 See Figure 4 V pin 1= 2.0V V pin 1= 2.0V At collector of external varicap drive transistor V pin 18 = 0.7V Pin 18 Current 100A
ppm/V mV p-p A A A A Nominal spread = +15% VOUT = 13.2V VOUT = VCC VIN = <0V VIN = <0V "Parallel resonant" crystal
Tamb=-200C to +800C, VCC = +4.5V to +5.5V. Reference frequency = 4MHz. Pin numbers refer to SP5026 (DP package). These characteristics are guaranteed by either test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated.
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Zarlink Semiconductor Inc.
Data Sheet Absolute Maximum Ratings
Absolute Maximum Ratings Table
SP5026
Parameter
Supply voltage Prescaler inputs Output ports Total port output current Prescaler DC offset Loop amplifier DC offset Crystal oscillator DC offset Data bus inputs Storage temperature Junction temperature DP 18 thermal resistance, chip-to-ambient DP 18 thermal resistance, chip-to-case MP 16 thermal resistance, chip-to-ambient MP 16 thermal resistance, chip-to-case Power consumption at 5V
All voltages are referred to VEE = 0V.
Pin SP5024
14 15,16 6-9 6-9 15,16 1,18 2 4,5,10
Pin SP5024S
12 13,14 6-9 6-9 13,14 1,16 2 4,5,10
Value Min
-0.3
Max
-6 2.5
Units
V Vp-p V V mA V V V V
0C 0C 0C/W 0C/W 0
Conditions
-0.3 -0.3
14 6 50
Port in off state Port in on state
-0.3 -0.3 -0.3 -0.7 -55
VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 +125 +150 78 24 111 41 275
With VCC applied
C/W
0C/W
mW
All ports off.
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